Op Code

M1 4

I2II2

I2I2

 

 

   The Branch Relative on Condition instruction examines the 2-bit condition code in the PSW and branches (or not) based on the value it finds. Operand 1 is a self-defining term which represents a 4-bit mask M1 (binary pattern) indicating the conditions under which the branch should occur. Operand 2 is the target address to which the branch will be made if the condition indicated in Operand 1 occurs.  Rather than representing the target as a base/displacement address, the number of half bytes from the current instruction to the target address is computed as a two’s complement integer and stored in the instruction as I2.

  

   BRC works in exactly like a BC except for the mechanism of specifying the target address –this is the address which replaces the current PSW instruction address field.  In the case of BRC, the target address is computed by doubling the two’s complement integer represented in I2, and adding the result to the address of the current instruction (not the PSW instruction address).  If the condition code has one of the values specified in the mask, the instruction address in the PSW is replaced with this “relative” address. Since I2 is a 16-bit two’s complement integer that represents a number of half bytes, this instruction can be used to branch forward (215 – 1) x 2 = 65534 bytes and backward 215  x 2 = 65536 bytes.

 

There are four possible values for the condition code:

 

Condition Code    Meaning

 

      00 

 

Zero or Equal

      01 

 

Low or Minus

      10 

 

High or Plus

      11 

 

Overflow 

 

   When constructing a mask for Operand 1, each bit ( moving from the high-order bit to the low-order bit ) represents one of the four conditions in the following order: Zero/Equal, Low/Minus,

High/Plus, Overflow. Consider the following instruction,

 

       BRC  8,THERE

 

   The first operand,”8”, is a decimal self-defining term and represents the binary mask B’1000’. Since the first bit is a 1, the mask indicates that a branch should occur on a zero or equal condition. Since the other bits are all 0, no branch will be taken on the other conditions. The first operand could be designated as any equivalent self-defining term. For example, the following instruction is equivalent to the one above.

 

       BRC  B’1000’,THERE

 

   When relative branching was introduced, new sets of extended mnemonics were also developed to replace the awkward construction of having to code a mask. The extended mnemonics are converted to BRC’s and are easier to code and read than using masks.  Here is a list of the branch relative extended mnemonics and the equivalent jump extended mnemonics.

 

 

Low/Min

High/Plus

Overflow

Decimal

Condition

Extended

Mnemonic 

0

0

0

0

JNOP

 

0

0

1

1

BRO,JO

 

0

1

0

2

BRH,JH

 

0

1

1

3

NO

MNEMONIC

1

0

0

4

BRL,JL

BRM,JM

1

0

1

5

NO

MNEMONIC

1

1

0

6

NO

MNEMONIC

1

1

1

7

BRNE,JNE

BNZ,JNZ

 

0

0

0

8

BRE,JE

BRZ,JZ

0

0

1

9

NO

MNEMONIC

0

1

0

10

NO

MNEMONIC

0

1

1

11

BRNL,JNL

BRNM,JNM

 

1

0

0

12

NO

MNEMONIC

1

0

1

13

BRNH,JNH

BRNP,JNP

 

1

1

0

14

NO

MNEMONIC

1

1

1

15

BRU,J

 

 

 

   Notice that branch relative mnemonics have equivalent jump mnemonics.  Simply replacing “BR” with “J” produces the equivalent mnemonic in most cases.  NOPs and unconditional branches are the exceptions.

 

   Using extended mnemonics we could replace the previous Branch Relative On Condition instruction (BRC  B’1000’,THERE) with any of the following instructions,

 

       BRZ  THERE

       JZ   THERE

       BRE  THERE

       JE   THERE

 

When the assembler processes BRZ, JZ, BRE, or JE it generates the mask as B’1000’. The table below indicates the possible mask values and the equivalent extended mnemonics.

 

 

 

      Tips

 

1)   BRC and the extended mnemonics that generate BRC’s represent a distinct improvement over BC’s.  Branch instructions specify their target addresses using base/displacement format, so for long programs, several base registers may be needed to cover all the target addresses.  With relative branches, the target address is specified as a number of halfwords from the current instruction.  No base registers are needed for target addresses. 

 

2)   Use jump (J) mnemonics instead of branch relative (BR) mnemonics.  Jumping is an accurate description of how these instructions operate.

 

3)   Abandon BC’s for any new code you develop – choose jumps.  You can also easily replace many older branch instructions with jumps as a way to reclaim the use of a registers that were given over to base/displacement addressing.  Registers are always at a premium, and saving a register by converting your code to use jumps is a no-brainer!

 

 

 

 

 

 

Some Unrelated Branch Relative on Conditions

 

       LTR  R8,R8       SET THE CONDITION CODE

       JP  HERE         JUMP IF CONDITION CODE IS POSITIVE 

       ...              OTHERWISE FALL THROUGH TO NEXT INSTRUCTION 

HERE   EQU *

       CLC  X,Y         SET THE CONDITION CODE

       JE     THERE     JUMP IF X = Y 

       ...          

THERE  EQU * 

OTHERWISE FALL THROUGH TO NEXT INSTRUCTION 

       CLC  X,Y  

SET THE CONDITION CODE

       BRE  YON 

JUMP IF X = Y  (Equivalent to JE)

       ...         

YON    EQU *

OTHERWISE FALL THROUGH TO NEXT INSTRUCTION 

 

Trying It Out in VisibleZ: 

1)       Load the program brc.obj from the \Codes directory and cycle through the first instruction.  The second instruction is BRC, and its immediate operand is X’FFFF’.  This number is -1 in two’s complement.  Why is the first instruction in the program highlighted in red?

2)       Load the program brc1.obj and cycle through the first three BRC instructions.  What are the masks of each instruction?  Do you understand why the branch was only taken on the third instruction?      

3)       Load the program brc2.obj.  Why does the fourth BRC branch forward?  Why does the fifth BRC branch backward?